In recent years, an integrated circuit (IC), which is widely used for a portable phone, a portable terminal, and the like and which has several hundreds of thousands to several millions of transistors and resistors formed over a silicon substrate having a size of about 5 mm square, has been playing an important role for downsizing and improving reliability of a device and for the mass production of the device.
In the case of designing a circuit used for an integrated circuit (IC) and the like, an amplifier circuit having a function to amplify a voltage or a current of a signal with small amplitude is designed. An amplifier circuit is used widely as an essential circuit for eliminating a distortion so that a circuit can operate stably.
Here, description is made on a differential amplifier circuit as an example of an amplifier circuit. A differential amplifier circuit is often used for a level shifter and an operational amplifier. Here, FIG. 6 shows a configuration example of a conventional level shifter and description is made on the configuration and operation thereof (see the conventional art of Patent Document 1: Japanese Patent Laid-Open No. 6-216753).
It is to be noted in this specification that each power source potential is referred to as VDD# and VSS# (# refers to a number). Here, VDD1, VDD2, VSS1, VSS2, and VSS3 are used and their levels are set to satisfy VSS3<VSS2<VSS1<VDD1<VDD2.
First, description is made on a configuration of a level shifter shown in FIG. 6(A). The level shifter shown in FIG. 6(A) shifts a high potential side while fixing a low potential side and outputs a signal with amplitude of a difference between a voltage level VSS1 and a voltage level VDD2 relatively to an input signal with amplitude of a difference between a voltage level VSS1 and a voltage level VDD1. This level shifter has the following configuration. A source region of a p-channel transistor 601 and a source region of a p-channel transistor 602 are both connected to a high potential power source (a power source potential VDD2). A gate electrode of the p-channel transistor 601 and a gate electrode of the p-channel transistor 602 are connected to each other and to a drain region of the p-channel transistor 602. A drain region of the p-channel transistor 601 is connected to a drain region of an n-channel transistor 603. A source region of the n-channel transistor 603 and a source region of an n-channel transistor are both connected to a low potential power source (a power source potential VSS1). Further, a first input signal in1 (a voltage thereof is expressed as Vin1) is inputted to a gate electrode of the n-channel transistor 603 and a second input signal in2 (a voltage thereof is expressed as Vin2) is inputted to a gate electrode of the n-channel transistor 604. It is to be noted that the second input signal in2 is an inverted signal of the first input signal in1. The drain region of the p-channel transistor 602 is connected to a drain region of the n-channel transistor 604, and an output signal out (a voltage thereof is expressed as Vout) is obtained from this node.
Next, description is made on a basic operation of the level shifter shown in FIG. 6(A). When a High signal is inputted as the first input signal in1, the n-channel transistor 603 becomes conductive and a drain potential thereof becomes VSS1. On the other hand, as the gate electrode and the drain region of the p-channel transistor 602 are connected to each other, the p-channel transistor 602 operates in a saturation region. Accordingly, a potential which is obtained by dividing a voltage between VDD2 and VDD1 by resistance of the n-channel transistor 604 and the p-channel transistor 602 is inputted to the gate electrode of the p-channel transistor 601. This potential is expressed as V601. When the first input signal in1 is a High signal, the second input signal is a Low signal; therefore, the n-channel transistor 604 becomes non-conductive. Accordingly, the potential V601 inputted to the gate electrode of the p-channel transistor 601 becomes higher in accordance with the power source potential VDD2. Therefore, the p-channel transistor 601 becomes non-conductive and a potential of the output signal out becomes VSS1.
When a Low signal is inputted as the first input signal in1, the n-channel transistor 603 becomes non-conductive. On the other hand, the second input signal becomes a High signal; therefore, the n-channel transistor 604 becomes conductive. Accordingly, the potential V601 inputted to the gate electrode of the p-channel transistor 601 becomes lower in accordance with the power source potential VSS1. Therefore, the p-channel transistor 601 becomes conductive and a potential of the output signal out becomes VDD2.
In this manner, the input signal with amplitude of a difference between the voltage level VSS1 and the voltage level VDD1 is converted into an output signal with amplitude of a difference between the voltage level VSS1 and the voltage level VDD2.
Next, description is made on a configuration of a level shifter shown in FIG. 6(B). The level shifter shown in FIG. 6(B) shifts a low potential side while fixing a high potential side and outputs a signal with amplitude of a difference between a voltage level VSS3 and the voltage level VSS1 relatively to an input signal with amplitude of a difference between the voltage level VSS2 and the voltage level VSS1. This level shifter has the following configuration. A source region of an n-channel transistor 607 and a source region of an n-channel transistor 608 are both connected to a low potential power source (a power source potential VSS3). A gate electrode of the n-channel transistor 607 and a gate electrode of the n-channel transistor 608 are connected to each other and to a drain region of the n-channel transistor 608 and a drain region of a p-channel transistor 606. A drain region of the n-channel transistor 607 is connected to a drain region of a p-channel transistor 605. A source region of the p-channel transistor 605 and a source region of the p-channel transistor 606 are both connected to a low potential power source (a power source potential VSS1). Further, a first input signal in1 is inputted to a gate electrode of the p-channel transistor 605 and a second input signal in2 is inputted to a gate electrode of the p-channel transistor 606. It is to be noted that the second input signal in2 is an inverted signal of the first input signal in1. An output signal out is obtained from the drain region of the first p-channel transistor 605.
Next, description is made on a basic operation of the level shifter shown in FIG. 6(B). When a Low signal is inputted as the first input signal in1, the p-channel transistor 605 becomes conductive and a drain potential of the p-channel transistor 605 becomes VSS1. On the other hand, as the gate electrode and the drain region of the n-channel transistor 608 are connected to each other, the n-channel transistor 608 operates in a saturation region. Accordingly, a potential obtained by dividing a voltage between VSS1 and VSS3 by resistance of the p-channel transistor 606 and the n-channel transistor 608 is inputted to the gate electrode of the n-channel transistor 607. This potential is expressed as V607. When the first input signal in1 is a Low signal, the second input signal becomes a High signal; therefore, the p-channel transistor 606 becomes non-conductive. Accordingly, the potential V607 inputted to the gate electrode of the n-channel transistor 607 becomes lower in accordance with the power source potential VSS3. Therefore, the n-channel transistor 607 becomes non-conductive and a potential of the output signal out becomes VSS1.
When a High signal is inputted as the first input signal in1, the p-channel transistor 605 becomes non-conductive. On the other hand, the second input signal becomes a Low signal; therefore, the p-channel transistor 606 becomes conductive. Accordingly, the potential V607 inputted to the gate electrode of the n-channel transistor 607 becomes higher in accordance with the power source potential VSS1. Therefore, the n-channel transistor 607 becomes conductive and a potential of the output signal out becomes VSS3.
In this manner, the input signal with amplitude of a difference between the voltage level VSS2 and the voltage level VSS1 is converted into an output signal with amplitude of a difference between the voltage level VSS3 and the voltage level VSS1.